This FPGA-based motherboard, part of the WARP project, is the central processing platform for prototyping and deploying wireless communications research. The modular system connects to RF interfaces to create a single 4-radio board capable of implementing next generation wireless algorithms. The board was designed and hand-routed as part of my M.S. thesis.
Some features of this 8in x 8in board design are:
- A 1517-pin Xilinx Virtex-4 FX100 FPGA, the largest production Virtex-4
- 18 copper layers for power distribution and signal routing
- Utilization of all 768 I/O available on the Virtex-4
- RF and analog data interfaces as part of a modular daughtercard standard, drawing power and I/O resource from the FPGA
- RF and logic clocks distributed from a central clocking board enabling syncing of multiple RF interfaces
- Multiple debug and data source interfaces for quick reprogramming, real-time debug and high bandwidth (3 Gigabit Ethernet) data input
- Up to 4GB and 64-bit wide bus of DDR2 SO-DIMM Memory where each byte-group is length-matched to within 1mil on the board, minimizing the phase difference between groups with a custom termination scheme.
- High-speed serial links (50 ohm impendence-matched differential pairs) sustaining data rates up to 6.25Gbps